2006-09-19 PLL IF curves

The electronics man of the Telis project has created a new macro (set of instructions in the flash memory of the Telis FPGA). The macro repeatedly steps up the harmonic mixer bias voltage and then varies (sweeps) the power of the LSU, the Local Source Unit.

I'm busy making a 3D plot of the result of this macro. It should look like this:

 LSU power (dBm)
   |
   |
   |
 15|---------------
   |
 10|---------------
   |
  5|---------------
   |_____________________
   0                 Harmonic Mixer Bias Voltage

The lines at 5, 10 and 15 dB must be colorized to indicate the PLL IF level. This is an output of the PLL, a voltage to indicate